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* add build to .dockerignore * test: only build one arch * add build to .gitignore * fix ccache path * filter amdgpu targets * only filter if autodetecting * Don't clobber gpu list for default runner This ensures the GPU specific environment variables are set properly * explicitly set CXX compiler for HIP * Update build_windows.ps1 This isn't complete, but is close. Dependencies are missing, and it only builds the "default" preset. * build: add ollama subdir * add .git to .dockerignore * docs: update development.md * update build_darwin.sh * remove unused scripts * llm: add cwd and build/lib/ollama to library paths * default DYLD_LIBRARY_PATH to LD_LIBRARY_PATH in runner on macOS * add additional cmake output vars for msvc * interim edits to make server detection logic work with dll directories like lib/ollama/cuda_v12 * remove unncessary filepath.Dir, cleanup * add hardware-specific directory to path * use absolute server path * build: linux arm * cmake install targets * remove unused files * ml: visit each library path once * build: skip cpu variants on arm * build: install cpu targets * build: fix workflow * shorter names * fix rocblas install * docs: clean up development.md * consistent build dir removal in development.md * silence -Wimplicit-function-declaration build warnings in ggml-cpu * update readme * update development readme * llm: update library lookup logic now that there is one runner (#8587) * tweak development.md * update docs * add windows cuda/rocm tests --------- Co-authored-by: jmorganca <jmorganca@gmail.com> Co-authored-by: Daniel Hiltgen <daniel@ollama.com>
35 lines
1.2 KiB
Plaintext
Vendored
35 lines
1.2 KiB
Plaintext
Vendored
#include "arange.cuh"
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static __global__ void arange_f32(float * dst, const int ne0, const float start, const float step) {
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// blockIDx.x: idx of ne0 / BLOCK_SIZE
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int nidx = threadIdx.x + blockIdx.x * blockDim.x;
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if (nidx >= ne0) {
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return;
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}
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dst[nidx] = start + step * nidx;
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}
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static void arange_f32_cuda(float * dst, const int ne0, const float start, const float step, cudaStream_t stream) {
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int num_blocks = (ne0 + CUDA_ARANGE_BLOCK_SIZE - 1) / CUDA_ARANGE_BLOCK_SIZE;
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arange_f32<<<num_blocks, CUDA_ARANGE_BLOCK_SIZE, 0, stream>>>(dst, ne0, start, step);
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}
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void ggml_cuda_op_arange(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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float * dst_d = (float *)dst->data;
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cudaStream_t stream = ctx.stream();
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GGML_ASSERT(dst->type == GGML_TYPE_F32);
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float start;
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float stop;
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float step;
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memcpy(&start, (float *)dst->op_params + 0, sizeof(float));
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memcpy(&stop, (float *)dst->op_params + 1, sizeof(float));
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memcpy(&step, (float *)dst->op_params + 2, sizeof(float));
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int64_t steps = (int64_t)ceil((stop - start) / step);
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GGML_ASSERT(ggml_nelements(dst) == steps);
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arange_f32_cuda(dst_d, dst->ne[0], start, step, stream);
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}
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